This application claims priority to Korean Patent Application No. 2004-006980, filed on Feb. 3, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to IC (integrated circuit) fabrication, and more particularly, to a shallow trench isolation (STI) structure with a liner layer that is converted from an initial material to a subsequent material for preserving the integrity of IC structures associated with the STI structure.
2. Description of the Related Art
Isolation technology is important for electrically isolating adjacent IC (integrated circuit) devices fabricated in a semiconductor substrate, especially with demand for higher integration and capacity of IC devices. Shallow trench isolation (STI) is particularly suited for the fabrication of highly integrated IC devices.
For STI, a STI trench is formed to surround an active region of a semiconductor substrate, and the STI trench is filled with insulating material. Further for such STI, an oxide layer is formed on the walls of the STI trench formed in a silicon substrate. In addition, a liner layer typically comprised of thin silicon nitride is also formed at the walls of the STI trench. After formation of such layers at the walls of the STI trench, the STI trench is filled with oxide such as an HDP (high density plasma) oxide.
With such STI, 4-giga-bit NAND flash memory devices have been developed with an active region pitch that is less than 150 nm. In such a NAND flash memory device, the width of the STI trench is a few tens of nanometers (such as 76 nm for example). Since the active region pitch is less than 150 nm, the STI trench is not filled in a single fill step. Rather, a multi-step process is employed to fill such a narrow width STI trench in the flash memory device as well as in DRAM or SRAM memory devices with small critical dimensions.
In the multi-step process for filling the STI trench, a mask layer pattern is formed through masking layers typically comprised of a silicon nitride layer and an oxide layer formed on a semiconductor substrate. The mask layer pattern is used as an etch mask as the STI trench is etched through the semiconductor substrate by anisotropic dry etching.
Thereafter, a first oxide layer is formed on the walls of the STI trench by thermal oxidation. In addition, a liner layer comprised of silicon nitride is then deposited on any exposed surfaces. Thereafter, a medium temperature oxide (MTO) deposition is performed to deposit a second oxide layer on any exposed surfaces.
After deposition of such layers, the STI trench is filled with a first dielectric fill material comprised of HDP (high density plasma) oxide or undoped silicate glass (USG). Thereafter, a wet etch-back process is performed such that the first dielectric fill material partially fills the STI trench. Subsequently, a third oxide layer from medium temperature oxide (MTO) deposition is deposited. Thereafter, the STI trench is completely filled with a second dielectric fill material also comprised of HDP oxide or USG.
In summary, the STI structure is formed by the multi-step process for filling the STI trench as follows: (1) STI trench formation→(2) first oxide layer by thermal oxidation of STI trench sidewall→(3) liner layer of silicon nitride→(4) second oxide layer by MTO deposition→(5) first dielectric fill material of HDP oxide or USG→(6) wet etch-back of first dielectric fill material→(7) third oxide layer by MTO deposition (may be omitted)→(8) second dielectric fill material of HDP oxide layer or USG.
Unfortunately, with the STI liner of silicon nitride, a dent is formed in the STI structure of the prior art from wet etching of the nitride layer forming the mask layer pattern. FIG. 1A shows an STI structure 20 of the prior art comprised of a dielectric fill material 22 within a STI trench 24. The dielectric fill material 22 is typically comprised of multiple fill materials formed in separate deposition steps in the multi-step process for filling the STI trench 24.
The STI trench 24 is patterned by etching through the semiconductor substrate 28 according to the opening in the mask layer pattern formed with an oxide layer 30 and a nitride layer 32. For simplicity in FIG. 1A, assume that a first oxide layer 34 and a liner layer 36 of silicon nitride are formed at the walls of the STI trench 24. Such layers 34 and 36 are formed at the walls of the STI trench 24 before the dielectric fill material 22 is deposited into the STI trench 24.
Referring to FIG. 1B, as the nitride layer 32 of the mask layer pattern is etched away in a wet-etch process, the top portion of the liner layer 36 also comprised of nitride is etched away. Thus, during any subsequent etch process for etching oxide, the exposed sidewall of the dielectric fill material 22 is etched away to form dents 38.
Such dents 38 cause deleterious effects and even failure in an adjacent transistor. Relative to DRAM or SRAM memory devices, a flash memory device is especially vulnerable to degradation of production yield from formation of such dents 38.
More specifically, for the transistor formed adjacent to any of such dents 38, the transistor exhibits a hump phenomenon whereby the transistor undesirably turns on, or whereby the threshold voltage of the transistor is decreased. In addition, bridging may occur in adjacent gate electrodes of transistors from residues of polysilicon comprising the gate electrodes of such transistors within the dents 38. In any case, the dents 38 deteriorate the electrical characteristics of the integrated circuit.
Therefore, especially for flash memory devices, the STI structure is desired to be formed with the liner layer 36 not being comprised of silicon nitride. An example process for forming such a STI structure includes the following steps: (1) STI trench formation→(2) forming a first oxide layer from thermal oxidation at walls of the STI trench→(3) forming a second oxide layer from MTO deposition→(4) filling the STI trench with a first dielectric fill material of HDP oxide or USG→(5) wet etch-back such that the first dielectric fill material partially fills the ST trench→(6) forming a third oxide layer from MTO deposition (may be omitted)→(7) filling the STI trench with a second dielectric fill material of HDP oxide or USG.
Unfortunately, a disadvantage of using just the oxide layers at the walls of the STI trench is that during the wet-etch process of step (5) above, a high-voltage (HV) oxide layer is damaged by the wet etch as illustrated in FIGS. 2A and 2B. Elements having the same reference number in FIGS. 1A and 2A refer to elements having similar structure and/or function. FIG. 2A shows a STI structure 40 formed with an oxide layer 42 formed at walls of the STI trench 24. The oxide layer 42 may be formed from multiple deposition processes with multiple oxide layers. A first dielectric fill material 44 is deposited to fill the STI trench 24 as in step (4) above.
Referring to FIGS. 2A and 2B, a wet etch-back is performed such that the first dielectric fill material 44 partially fills the STI trench 24, as in step (5) above. Typically, the first dielectric fill material 44 is comprised of an oxide. Thus, during the wet etch-back for etching the first dielectric fill material 44, the upper portion of the oxide layer 42 is also etched away. In addition, side portions 46 of the oxide layer 30 forming the mask layer pattern are also etched away from being exposed in FIG. 2B. The oxide layer 30 of the mask layer pattern may also form the HV (high voltage) gate dielectric for transistors in a peripheral circuit region of a memory device. In that case, such etching of the side portions 46 of the HV oxide layer 30 results in operational degradation of such transistors.
Thus, a mechanism for forming an STI structure is desired with preservation of the integrity of the IC structures 22 of FIGS. 1B and 30 of FIG. 2B.